1. Field of the Invention
The present invention relates to a data processing system including a master and a slave which perform data communication therebetween.
2. Description of the Prior Art
In a system LSI including a plurality of masters which share one or more slaves via buses, the function of performing a master reset when a fault occurs in some of the masters during an operation of the system has to be provided. Herein, a master is a microprocessor, DSP (Digital Signal Processor), DMA (Direct Memory Access) controller, or the like and a slave is a memory, peripheral I/O (input/output) controller, or the like.
According to a known technique disclosed in Japanese Laid-Open Publication No. H11-312102, when a fault occurs in one of devices connected to a bus and thus is to be reset, the system is recovered from the fault in such a manner that all the devices are temporarily stopped first, fault information is collected, and a resister that needs resetting is reset and cleared.
However, when one of masters operating a system has to be reset and, in order to recover the system, operations of all the masters are temporarily stopped, the other ones of the masters which are irrelevant to the reset are influenced, so the performance of the system is largely affected.
In addition, to stop an operation of a master and increase the speed of a recovery operation, a special function has to be provided additionally to a master and a slave. In such a case, for example, if IP (Intellectual Property) owned by another company is used in a master and a slave or if it is difficult to make modifications for some other reasons, the problems can not be solved.
Moreover, even in a system in which a single master performs data communication with a slave, if a command which has been already issued by the master in a state of being incapable of executing data transmission remains in the slave, some error occurs in a system recovery operation.